View GMS97C1051-24D_2580417.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

8-bit cmos microcontorller gms97c2051/l2051 hyundai microelectonics 1 features compatible with mcs-51 tm products 2 kbytes of programmable eprom 4.25v to 5.5v operating range (gms97c2051) 2.70v to 3.6v operating range (gms97l2051) version for 12mhz / 24 mhz operating frequency (gms97c2051) only 12mhz operating frequency (gms97l2051) two-level program memory lock with encryption array 128 bytes sram 15 programmable i/o lines two 16-bit timer/counters programmable serial usart five interrupt sources direct led drive outputs on-chip analog comparator low power idle and power down modes description the gms97c2051/l2051 is a high-performance cmos 8-bit microcontroller with 2kbytes of programmable eprom. the device is compatible with the industry standard mcs-51 tm instruction set and pinout. the hyun- dai microelectronics gms97c2051/l2051 is a powerful microcontroller which provides a highly flexible and cost effective solution to many embedded control applications. the gms97c2051/l2051 provides the following standard features: 2kbytes of eprom, 128 bytes of ram, 15 i/o lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, a precision analog comparator, on-chip oscillator and clock circuitry. in addition, the gms97c2051/l2051 supports two software selectable power saving modes. the idle mode stops the cpu while allowing the ram, timer/counters, serial port and interrupt system to continue functioning. the power down mode saves the ram contents but freezes the oscillator disabling all other chip functions until the next hardware reset. pin configuration pdip/sop ( t0 ) p3.4 vcc p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 (ain1) p1.0 (ain0) p3.7 rst (rxd) p3.0 (txd) p3.1 xtal2 xtal1 ( int1 ) p3.3 (t1) p3.5 gnd 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 ( int0 ) p3.2
gms97c2051/l2051 8-bit cmos microcontroller hyundai microelectronics 2 block diagram vcc gnd p1.0-p1.7 ram addr ram stack pointer pc incrementer program counter acc eprom program address register buffer dptr tmp1 tmp2 psw b register interrupt, serial port and timer blocks osc port 3 latch port 1 latch timing and control instruction register + _ port 1 drivers port 3 drivers rst p3.0-p3.5 p3.7 analog comparator alu
8-bit cmos microcontorller gms97c2051/l2051 hyundai microelectonics 3 pin description vcc supply voltage. gnd ground. port 1 port 1 is an 8-bit bidirectional i/o port. port pins p1.2 to p1.7 provide internal pullups. p1.0 and p1.1 re- quire external pullups. p1.0 and p1.1 also serve as the positive input (ain0) and the negative input (ain1), respectively, of the on-chip precision analog compara- tor. the port 1 output buffers can sink 10ma and can drive led displays directly. when 1s are written to port1 pins, they can be used as inputs. when pins p1.2 to p1.7 are used as inputs and are externally pulled low, they will source current (i il ) because of the inter- nal pullups. port 1 also receives code data during eprom pro- gramming and program verification. port3 port 3 pins p3.0 to p3.5, p3.7 are seven bidirectional i/o pins with internal pullups. p3.6 is hard-wired as an input to the output of the on-chip comparator and is not accessible as a general purpose i/o pin. the port 3 output buffers can sink 10ma. when 1s are written to port 3 pins they are pulled high by the internal pul- lups and can be used as inputs. as inputs, port 3 pins that are externally being pulled low will source current (i il ) because of the pullups. port 3 also serves the functions of various special fea- ture of the gms97c2051 as listed below: port pin alternate functions p3.0 p3.1 p3.2 p3.3 p3.4 p3.5 rxd ( serial input port ) txd ( serial output port ) int0 ( external interrupt 0 ) int1( external interrupt 1 ) t0 ( timer 0 external input ) t1 ( timer 0 external input ) port 3 also receives some control signals for eprom programming and programming verification. rst reset input. all i/o pins are reset to 1s as soon as rst goes high. holding the rst pin high for two machine cycles while the oscillator is running resets the device. this pin is also receives the 12.75v programming supply voltage ( vpp ) during eprom programming. xtal1 input to the inverting oscillator amplifier and input to the internal clock operating circuit. xtal2 output from the inverting oscillator amplifier. recommended oscillator circuit xtal1 and xtal2 are the input and output, respec- tively, of an inverting amplifier which can be config- ured for use as an on-chip oscillator, as shown in fig- ure 1. to drive the device from an external clock source, xtal2 should be left unconnected while xtal1 is driven as shown in figure 2 . figure 1. oscillator connections c2 c1 xtal2 xtal1 gnd notes: c1, c2 = 30pf 10pf for crystals ( include stray capacitance ) figure 2. external clock drive configuration xtal2 xtal1 gnd external oscillator signal nc
gms97c2051/l2051 8-bit cmos microcontroller hyundai microelectronics 4 special function registers a map of the on-chip memory area called the special function register (sfr) space is shown in the table1, table 2 and table 3 . note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. user software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. in that case, the reset or inactive values of the new bits will always be 0. table 1 . gms97c2051/l2051 sfr map and reset values 0f8h 0ffh 0f0h b 00000000 0f7h 0e8h 0efh 0e0h acc 00000000 0e7h 0d8h 0dfh 0d0h psw 00000000 0d7h 0c8h 0cfh 0c0h 0c7h 0b8h ip xxx00000 0bfh 0b0h p3 11111111 0b7h 0a8h ie 0xx00000 0afh 0a0h 0a7h 98h scon 00000000 sbuf xxxxxxxx 9fh 90h p1 11111111 97h 88h tcon 00000000 tmod 00000000 tl0 00000000 tl1 00000000 th0 00000000 th1 00000000 8fh 80h sp 00000111 dpl 00000000 dph 00000000 pcon 0xxx0000 87h
8-bit cmos microcontorller gms97c2051/l2051 hyundai microelectonics 5 table 2 . bit assignment of sfrs address register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 81 h sp 82 h dpl 83 h dph 87 h pcon smod - - - gf1 gf0 pd idle 88 h tcon tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 89 h tmod gate c / t m1 m0 gate c / t m1 m0 8a h tl0 8b h tl1 8c h th0 8d h th1 90 h p1 98 h scon sm0 sm1 sm2 ren tb8 rb8 ti ri 99 h sbuf a8 h ie ea - - es et1 ex1 et0 ex0 b0 h p3 b8 h ip - - - ps pt1 px1 pt0 px0 d0 h psw cy ac f0 rs1 rs0 ov f1 p e0 h acc f0 h b - : this bit location is reserved bit manipulation is available bit manipulation is not available
gms97c2051/l2051 8-bit cmos microcontroller hyundai microelectronics 6 table 3 . sfr lists and their addresses symbol name address * acc * b dph dpl * psw sp accumulator b register data pointer high byte data pointer low byte program status word stack pointer e0 h f0 h 83 h 82 h d0 h 81 h * ie * ip interrupt enable control interrupt priority control a8 h b8 h * p1 * p3 port 1 port 3 90 h b0 h * scon sbuf serial control serial data buffer 98 h 99 h * tcon th0 th1 tl0 tl1 * tmod timer/counter control timer/counter 0 high bytes timer/counter 1 high bytes timer/counter 0 low bytes timer/counter 1 low bytes timer/counter mode control 88 h 8c h 8d h 8a h 8b h 89 h * = bit addressable sfr timer/counter 0 and 1 the gms97c2051/l2051 has two 16-bit timer/ counter register : timer0 and timer1 . as a timer, the register is incremented every machine cycle. thus, the register counts machine cycle. since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. as a counter, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin p3.4/t0 and p3.5/t1. since 2 machine cycles are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator fre- quency. external inputs p3.2/int0 and 3.3/int1 can be programmed to function as a gate to facili- tate pulse width measurements. timer/counter 0 and 1 can be used in four operating modes as listed in table 4 . figure 3 illustrates the input clock logic. table 4 . timer / counter 0 and 1 operating modes mode description tmod gate c / t m1 m0 0 8-bit timer/counter with 5-bit prescaler 00 1 16-bit timer/counter 01 2 8-bit auto-reload timer/counter 10 3 (timer 0) : tl0 is an 8-bit timer/counter controlled by the standard timer 0 control bits, th0 is an 8-bit timer and is controlled by timer 1 (timer 1) : stop 11
8-bit cmos microcontorller gms97c2051/l2051 hyundai microelectonics 7 figure 3 . time/counter 0 and 1 input clock logic serial interface (usart) the serial port is full duplex, meaning it can trans- mit and receive simultaneously. and it can operate in four modes (one synchronous mode, three asyn- chronous mode) as illustrated in table 5 . the possi- ble baud rates can be calculated using the formulas given in table 6 . table 5 . usart operating modes mode scon baud rate description sm0 sm1 0 0 0 fosc / 12 ( fixed ) shift register : serial data enters and exits through rxd. txd outputs the shift clock. eight data bits are transmitted / received, with the lsb first. 1 0 1 set by timer ( variable ) 8-bit uart : ten bits are transmitted through txd, or received through rxd a start bit (0), 8 data bits (lsb first), and a stop bit (1) 2 1 0 fosc / 64 or fosc / 32 ( fixed ) 9-bit uart : eleven bits are transmitted through txd, or received through rxd a start bit (0), 8 data bits (lsb first), a programmable ninth data bit , and a stop bit (1) 3 1 1 set by timer ( variable ) 9-bit uart : the same as mode 2 except the variable baud rate. fosc 12 p3.4/t0 p3.5/t1 max fosc/24 tr 0/1 tcon gate tmod =1 1 & 0 1 fosc/12 timer 0/1 input clock control c/t tmod p3.2/int0 p3.3/int1
gms97c2051/l2051 8-bit cmos microcontroller hyundai microelectronics 8 table 6 . formulas for calculating baud rates baud rate generated from serial port mode baud rate oscillator 0 2 fosc / 12 (2 smod x fosc) / 64 timer1 (timer1 mode2) 1 , 3 1 , 3 (2 smod x timer1 overflow rate) / 32 (2 smod x fosc) / [32 x 12 x (256-th1)] interrupt system the gms97c2051/l2051 provides 5 interrupt sources ( two external interrupts, two timer inter- rupts and serial port interrupt ) with two priority levels. figure 4 gives a general overview of the interrupt sources and illustrates the request and control flags. a low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low priority interrupt. a high-priority interrupt cannot be interrupted by any other interrupt source. if two requests of different priority levels are re- ceived simultaneously, the request of higher priority is serviced. if requests of the same prior- ity level are received simultaneously, an internal polling sequence determines which request is serv- iced. thus within each priority level there is a second priority structure determined by the polling sequence like table 8 . figure 4 . interrupt request sources timer 1 overflow et1 ie.3 pt1 ip.3 tf1 tcon.7 it0 tcon.0 tcon.1 ie0 ex0 ie.0 px0 ip.0 p3.2/ int0 ea ie.7 it1 tcon.2 tcon.3 ie1 ex1 ie.2 px1 ip.2 p3.3/ int1 tf0 tcon.5 timer 0 overflow et0 ie.1 pt0 ip.1 1 r1 scon.0 usart scon.1 t1 es ie.4 ps ip.4 high priority low priority
8-bit cmos microcontorller gms97c2051/l2051 hyundai microelectonics 9 table 7 . interrupt sources and their corresponding interrupt vectors interrupt source vector address external interrupt 0 timer0 external interrupt 1 timer1 serial port interrupt system reset ie0 tf0 ie1 tf1 ri + ti rst 0003h 000bh 0013h 001bh 0023h 0000h table 8 . interrupt priority-within-level interrupt source priority external interrupt 0 timer0 interrupt external interrupt 1 timer1 interrupt serial port interrupt ie0 tf0 ie1 tf1 ri + ti highest lowest restrictions on certain instructions the gms97c2051/l2051 is an economical and cost- effective member of hyundai microelectronics growing family of microcontrollers. it contains 2kbytes of eprom program memory. it is fully compatible with the mcs-51 architecture, and can be programmed using the mcs-51 instruction set. how- ever, there are a few considerations one must keep in mind when utilizing certain instructions to program this device. 1. branching instructions: lcall, ljmp, acall, ajmp, sjmp, jmp @a+dptr these unconditional branching instructions will ex- ecute correctly as long as the programmer keeps in mind that the destination branching address must fall within the physical boundaries of the program memory size (locations 00h to 7ffh for the gms97c2051/l2051). violating the physical space limits may cause unknown program behavior. cjne [...], djnz [...], jb, jnb, jc, jnc, jbc, jz, jnz with these conditional branching instructions the same rule above applies. again, violating the memory boundaries may cause erratic execution. for applications involving interrupts the normal inter- rupt service routine address locations of the 80c51 family architecture have been preserved. 2. movx-related instructions, data memory: the gms97c2051/l2051 contains 128 bytes of inter- nal data memory. thus, in the gms97c2051/l2051 the stack depth is limited to 128 bytes, the amount of available ram. external data memory access is not supported in this device, nor is external pro- gram memory execution. therefore, no movx [...] instructions should be included in the program. a typical 80c51 assembler will still assemble instruc- tions, even if they are written in violation of the restric- tions mentioned above. it is the responsibility of the controller user to know the physical features and limi- tations of the device being used and adjust the instruc- tions used correspondingly.
gms97c2051/l2051 8-bit cmos microcontroller hyundai microelectronics 10 idle mode in idle mode, the cpu puts itself to sleep while all the on-chip peripherals remain active. the mode is in- voked by software. the content of the on-chip ram and all the special functions registers remain unchanged during this mode. the idle mode can be terminated by any enabled interrupt or by a hardware reset. p1.0 and p1.1 should be set to 0 if no external pullups are used, or set to 1 if external pullups are used. it should be noted that when idle is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. on-chip hardware inhibits access to internal ram in this event, but access to the port pins is not inhibited. to eliminate the possibility of an unexpected write to a port pin when idle is terminated by reset, the instruc- tion following one that invokes idle should not be one that writes to a port pin or to external memory. power down mode gms97c2051/l2051 have two power saving modes, idle and power down. the bits pd and idle of the register pcon select the power down mode and the idle mode, respectively. if 1s are written to pd and idle at the same time, pd takes precedence. table 9 gives a general overview of the power saving modes. in the power down mode of operation, v cc can be re- duced to minimize power consumption. it must be ensured, however, that vcc is not reduced before the power down mode is invoked, and that vcc is restored to its normal operating level, before the power down mode is terminated. the reset signal that terminates the power down mode also restarts the oscillator. the reset should not be activated before vcc is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. ( similar to power-on reset ). table 9 . power saving modes overview mode ex. instruction to enter to terminate remarks idle mode orl pcon, #01h enabled interrupt, hardware reset - cpu is gated off - cpu status registers maintain their data. - peripherals are active power-down mode orl pcon, #02h hardware reset - oscillator stops - contents of on-chip ram and sfrs are maintained - reset redefines all the sfrs but does not change the on-chip ram
8-bit cmos microcontorller gms97c2051/l2051 hyundai microelectonics 11 programming the eprom the gms97c2051/l2051 is programmed by using a modified quick-pulse programming tm algorithm. it differs from older methods in the value used for v pp (programming supply voltage) and in the width and number of the p3.2( prog ) . the gms97c2051/l2051 contains two signature bytes that can be read and used by an eprom pro- gramming system to identify the device. the signature bytes identify the device as an manufactured by hme . table 10 shows the logic levels for reading the signa- ture byte, and for programming the program memory, the encryption table, and the security bits. the circuit configuration and waveforms for quick-pulse pro- gramming are shown in figures 5 and figure 8. figure 6 shows the circuit configuration for normal program memory verification. eprom programming and verification internal address counter : the gms97c2051/l2051 contains an internal eprom address counter which is always set to 07ffh on the rising edge of rst after setting p3.0 to h and is ad- vanced by applying continuous level transition to pin p3.0. programming algorithm : to program the gms97c2051/l2051, the following sequence is recommended. 1. power-up sequence apply power between v cc and gnd pins with crystal oscillation. set p3.0 to h. set rst to gnd. with all other pins floating, wait for greater than 10ms. 2. set pin rst to h and pin p3.2 to h. 3. apply the appropriate combination of h or l logic levels to pins p3.3, p3.4, p3.5, p3.7 to select one of the programming operations shown in the eprom programming modes. ( table 10 ). to program and verify the array 4. the p3.0 level is pulled l and apply data for code byte at location 0000h to p1.0 to p1.7 5. raise rst to 12.75v to enable pr ogramming. 6. the p3.2( prog ) is pulsed low 10 times as shown in figure 8 . each programming pulse is low for 100us( 10us) and high for a minimum of 10us. 7. to verify the programmed data, lower rst from 12.75v to logic h level and set pins p3.3 to p3.7 to the appropriate levels. output data can be read at the port p1 pins. at this time p3.0 should not be changed. 8. to program a byte at the next address location, p3.0 level transition is needed to advance the internal address counter. apply new data to the port p1 pins. 9. repeat step 5 through 8, changing data and advancing the address counter for the entire 2k bytes array. program verify : if lock bits lb1 and lb2 have not been programmed, code data can be read back via port p1 pins. 1. set the internal address counter to 07ffh by bringing rst from l to h and reset the internal address counter to 0000h by bringing p3.0 from h to l. 2. apply the appropriate control signals for read code data to pins p3.3, p3.4, p3.5, p3.7 and read the output data at the port p1 pins. 3. the p3.0 level transition is taken to advance the internal address counter. 4. read the next code data byte at the port p1 pins. 5. repeat step 3 and 4 until the entire array is read. program memory lock bits the two-level program lock system consists of 2 lock bits and a 32-byte encryption array which are used to protect the program memory against software piracy. encryption array : within the eprom array are 32 bytes of encryption array that are initially unprogrammed (all 1s). every time that a byte is addressed during a verify, address lines are used to select a byte of the encryption array. this byte is then exclusive-nored (xnor) with the code byte, creating an encrypted verify byte. the algorithm, with the array in the unprogrammed state (all 1s), will return the code in its original, un- modified form. it is recommended that whenever the encryption array is used, at least one of the lock bits be programmed as well.
gms97c2051/l2051 8-bit cmos microcontroller hyundai microelectronics 12 lock bit protection modes program lock bits lb1 lb2 protection type 1 u u no program lock features. 2p u further programming of the eprom is disabled. 3p p same as mode 2, also verify is disabled. reading the signature bytes : the signature bytes are read by the same procedure as a normal verification of locations 000h and 001h, except that p3.5 and p3.7 need to be pulled to a logic low. manufacturer id: (00h) = e0h ( indicates manufactured by hei ) device id: (01h) = 26h ( indicates gms97c2051/l2051 ) u : unprogrammed, p : programmed eprom programming modes table 10 . eprom programming modes mode rst p3.2/ prog p3.3 p3.4 p3.5 p3.7 read signature 1 1 0 0 0 0 program code data vpp 0 1 1 1 verify code data 1 1 0 0 1 1 pgm encryption table vpp 0 1 0 1 pgm encryption bit1 vpp 1 1 1 1 pgm encryption bit vpp 1 1 0 0 notes:1. '0' = valid low, '1' = valid high for that pin. 2. vpp = 12.75 v 0.25 v 3. vcc = 5 v 10 % during program- ming and verification. 4. p3.2/ prog receives 10 programming pulses while vpp is held at 12.75v. each program- ming pulse is low for 100us ( 10us) and high for a minimum of 10us.
8-bit cmos microcontorller gms97c2051/l2051 hyundai microelectonics 13 figure 5. programming the eprom memory p3.0 p3.2 p3.3 p3.4 p3.5 p3.7 v cc p1 pgm data vpp xtal2 gnd to increment address counter see eprom programming 4~6mhz modes tables prog 5v gms97c1051 rst xtal1 figure 6. verifying the eprom memory p3.0 p3.2 p3.3 p3.4 p3.5 p3.7 v cc p1 pgm data 5v 5v xtal2 gnd to increment address counter see eprom programming 4~6mhz modes tables 5v gms97c1051 rst xtal1 eprom programming and verification characteristics table 11 . eprom programming and verification characteristics parameter symbol min max units programming supply voltage v pp 12.5 13.0 v programming supply current i pp 50 ma oscillator frequency 1 / t clcl 46mhz address setup to prog low t avgl 48 t clcl data setup to prog low t dvgl 48 t clcl data hold after prog t ghdx 48 t clcl p3.4 ( enable ) high to v pp t ehsh 48 t clcl v pp setup to prog low t shgl 10 us v pp hold after prog t ghsl 10 us prog width t glgh 90 110 us prog high to prog low t ghgl 10 us p3.4 ( enable ) low to data valid t elqv 48 t clcl data float after p3.4 ( enable ) t ehqz 0 48 t clcl t a = 21 to 27 , v cc = 5.0 10%
gms97c2051/l2051 8-bit cmos microcontroller hyundai microelectronics 14 eprom programming and verification waveforms figure 7 . eprom programming and verification data in data out address (n+1) address (n) t ehsh t ghgl vpp logic 1 logic 0 rst (vpp) p3.4 (enable) port1 p3.2 (prog) p3.0 t ghsl t dvgl t ghdx t glgh t avgl t shgl t elqv t eh q z programming verification figure 8 . programming waveform p3.2/ prog 10 pulses 100 10 10 min p3.2/ prog
8-bit cmos microcontorller gms97c2051/l2051 hyundai microelectonics 15 absolute maximum ratings ambient temperature under bias (t a .)....................... - 40 to + 85 storage temperature (t st ) ..... -65 to + 150 voltage on v cc pin with respect to ground(v ss )...........-0.5v to 6.5v voltage on any pin with respect to ground(v ss )... -0.5v to v cc +0.5v input current on any pin during overload condition.........-10ma to +10ma absolute sum of all input current during overload condition................... | 100 ma | note : stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for longer periods may affect device reliability. during overload conditions (v in > vcc or v in < vss ) the voltage on vcc pins with respect to ground (vss) must not exceed the values defined by the absolute maximum ratings.
gms97c2051/l2051 8-bit cmos microcontroller hyundai microelectronics 16 d.c. characteristics (5v version) vcc = 4.25v to 5.5v, vss= 0v, t a = 0 o c to 70 o c for the gms97c2051/c1051 parameter symbol limit values unit test min max condition input low voltage v il -0.5 0.2vcc-0.1 v input high voltage (except xtal1, rst) v ih 0.5vcc-0.1 vcc+0.5 v input high voltage (xtal1, rst) v ih1 0.7vcc vcc+0.5 v output low voltage (ports 1,3) v ol 0.45 v i ol =10ma,vcc=5v output high voltage (ports 1,3) v oh 2.4 0.75vcc 0.9vcc vi oh = -80ua, vcc=5v 10% i oh = -30ua i oh = -12ua logical 0 input current (ports 1,3) i il -50 ua v in =0.45v logical 1-to-0 transition current (ports 1,3) i tl -750 ua v in =2v input leakage current (port p1.0, p1.1) i li 1ua ua 0 8-bit cmos microcontorller gms97c2051/l2051 hyundai microelectonics 17 d.c. characteristics (3v version) vcc = 2.7v to 3.6v, vss= 0v, t a = 0 o c to 70 o c for the gms97l2051/l1051 parameter symbol limit values unit test min max condition input low voltage v il -0.5 0.2vcc-0.1 v input high voltage (except xtal1, rst) v ih 0.5vcc-0.1 vcc+0.5 v input high voltage (xtal1, rst) v ih1 0.7vcc vcc+0.5 v output low voltage (ports 1,3) v ol 0.45 v i ol =6ma,vcc=2.7v output high voltage (ports 1,3) v oh 0.75vcc 0.9vcc vi oh = -30ua i oh = -12ua logical 0 input current (ports 1,3) i il -50 ua v in =0.45v logical 1-to-0 transition current (ports 1,3) i tl -750 ua v in =2v input leakage current (port p1.0, p1.1) i li 1ua ua 0 gms97c2051/l2051 8-bit cmos microcontroller hyundai microelectronics 18 external clock drive waveforms t chcx t clcl t clcx t chcx t clch 0.7 v cc 0.2 v cc - 0.1v 0.45v v cc - 0.5 v t chcl external clock drive symbol parameter gms97l2051/l1051 gms97c2051/c1051 min max min max units 1/t clcl oscillator frequency 0 12 0 24 mhz t clcl clock period 83.3 41.6 ns t chcx high time 30 15 ns t clcx low time 30 15 ns t clch rise time - 20 - 20 ns t chcl fall time - 20 - 20 ns ac testing input/output waveforms (1) v cc - 0.5v 0.45v 0.2v cc + 0.9v test points 0.2v cc - 0.1v note: 1. ac inputs during testing are driven at v cc - 0.5v for a logic 1 and 0.45v for a logic 0. timing measurements are made at v ih min. for a logic 1 and v il max. for a logic 0. float waveforms (1) v load + 0.1v v load v load - 0.1v v ol + 0.1v v ol + 0.1v timing reference points note: 1. for timing purposes, a port pin is no longer floating when a 100mv change from load voltage occurs. a port pin begins to float when a 100mv change from the loaded v oh /v ol level occurs.
8-bit cmos microcontorller gms97c2051/l2051 hyundai microelectronics 19 package dimension 20 pdip 20 sop unit : mm ( inch )
gms97c2051/l2051 8-bit cmos microcontroller hyundai microelectronics 20 ordering information speed ( mhz) power supply ordering code package operation range 12 2.7v to 3.6v gms97l2051 20 pdip gms97l2051-d 20 sop 4.25v to 5.5v gms97c2051 20 pdip commercial gms97c2051-d 20 sop (0 to 70 ) 24 4.25v to 5.5v gms97c2051-24 20 pdip gms97c2051-24d 20 sop package type 20 pdip 20 lead, 0.300 wide, plastic dual inline package (pdip) 20 sop 20 lead, 0.300 wide, plastic gull wing small outline (sop)
8-bit cmos microcontorller gms97c1051/l1051 hyundai microelectronics 21 features compatible with mcs-51 tm products 1 kbytes of programmable eprom 4.25v to 5.5v operating range (gms97c1051) 2.70v to 3.6v operating range (gms97l1051) version for 12mhz / 24 mhz operating frequency (gms97c1051) only 12mhz operating frequency (gms97l1051) two-level program memory lock with encryption array 64 bytes sram 15 programmable i/o lines one 16-bit timer/counter three interrupt sources direct led drive outputs on-chip analog comparator low power idle and power down modes description the gms97c1051/l1051 is a high-performance cmos 8-bit microcontroller with 1kbytes of programmable eprom. the device is compatible with the industry standard mcs-51 tm instruction set and pinout. the hyundai microelectronics gms97c1051/l1051 is a powerful microcontroller which provides a highly flexi- ble and cost effective solution to many embedded control applications. the gms97c1051/l1051 provides the following standard features: 1kbytes of eprom, 64 bytes of ram, 15 i/o lines, 16-bit timer/counter, a three vector two-level interrupt architecture, a precision analog comparator, on-chip oscillator and clock circuitry. in addition, the gms97c1051/l1051 supports two software selectable power saving modes. the idle mode stops the cpu while allowing the ram, timer/counters, serial port and interrupt system to continue functioning. the power down mode saves the ram contents but freezes the oscillator disabling all other chip functions until the next hardware reset. pin configuration ( t0 ) p3.4 vcc p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 (ain1) p1.0 (ain0) p3.7 rst p3.0 p3.1 xtal2 xtal1 ( int1 ) p3.3 p3.5 gnd 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 pdip/sop ( int0 ) p3.2
gms97c1051/l1051 8-bit cmos microcontroller hyundai microelectronics 22 block diagram vcc gnd p1.0-p1.7 ram addr ram stack pointer pc incrementer program counter acc eprom program address register buffer dptr tmp1 tmp2 psw b register interrupt , timer blocks osc port 3 latch port 1 latch timing and control instruction register + _ port 1 drivers port 3 drivers rst p3.0-p3.5 p3.7 analog comparator alu
8-bit cmos microcontorller gms97c1051/l1051 hyundai microelectronics 23 pin description vcc supply voltage. gnd ground. port 1 port 1 is an 8-bit bidirectional i/o port. port pins p1.2 to p1.7 provide internal pullups. p1.0 and p1.1 re- quire external pullups. p1.0 and p1.1 also serve as the positive input (ain0) and the negative input (ain1), respectively, of the on-chip precision analog compara- tor. the port 1 output buffers can sink 10ma and can drive led displays directly. when 1s are written to port1 pins, they can be used as inputs. when pins p1.2 to p1.7 are used as inputs and are externally pulled low, they will source current (i il ) because of the inter- nal pullups. port 1 also receives code data during eprom pro- gramming and program verification. port3 port 3 pins p3.0 to p3.5, p3.7 are seven bidirectional i/o pins with internal pullups. p3.6 is hard-wired as an input to the output of the on-chip comparator and is not accessible as a general purpose i/o pin. the port 3 output buffers can sink 10ma. when 1s are written to port 3 pins they are pulled high by the internal pul- lups and can be used as inputs. as inputs, port 3 pins that are externally being pulled low will source current (i il ) because of the pullups. port 3 also serves the functions of various special fea- ture of the gms97c1051/l1051 as listed below: port pin alternate functions p3.2 p3.3 p3.4 int0 (external interrupt 0) int1 (external interrupt 1) t0 (timer 0 external input) port 3 also receives some control signals for eprom programming and programming verification. rst reset input. all i/o pins are reset to 1s as soon as rst goes high. holding the rst pin high for two machine cycles while the oscillator is running resets the device. this pin is also receives the 12.75v programming supply voltage ( vpp ) during eprom programming. xtal1 input to the inverting oscillator amplifier and input to the internal clock operating circuit. xtal2 output from the inverting oscillator amplifier. recommended oscillator circuit xtal1 and xtal2 are the input and output, respec- tively, of an inverting amplifier which can be config- ured for use as an on-chip oscillator, as shown in fig- ure 1. to drive the device from an external clock source, xtal2 should be left unconnected while xtal1 is driven as shown in figure 2 . figure 1. oscillator connections c2 c1 xtal2 xtal1 gnd notes: c1, c2 = 30pf 10pf for crystals ( include stray capacitance ) figure 2. external clock drive configuration gnd external oscillator signal nc xtal2 xtal1
gms97c1051/l1051 8-bit cmos microcontroller hyundai microelectronics 24 special function registers a map of the on-chip memory area called the special function register (sfr) space is shown in the table1, table 2 and table 3 . note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. user software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. in that case, the reset or inactive values of the new bits will always be 0. table 1 . gms97c1051/l1051 sfr map and reset values 0f8h 0ffh 0f0h b 00000000 0f7h 0e8h 0efh 0e0h acc 00000000 0e7h 0d8h 0dfh 0d0h psw 00000000 0d7h 0c8h 0cfh 0c0h 0c7h 0b8h ip xxx00000 0bfh 0b0h p3 11111111 0b7h 0a8h ie 0xx00000 0afh 0a0h 0a7h 98h 9fh 90h p1 11111111 97h 88h tcon 00000000 tmod 00000000 tl0 00000000 th0 00000000 8fh 80h sp 00000111 dpl 00000000 dph 00000000 pcon 0xxx0000 87h
8-bit cmos microcontorller gms97c1051/l1051 hyundai microelectronics 25 table 2 . bit assignment of sfrs address register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 81 h sp 82 h dpl 83 h dph 87 h pcon----gf1gf0pdidle 88 h tcon - - tf0 tr0 ie1 it1 ie0 it0 89 h tmod----gatec / t m1 m0 8a h tl0 8c h th0 90 h p1 a8 h ieea----ex1et0ex0 b0 h p3 b8 h ip -----px1pt0px0 d0 h psw cy ac f0 rs1 rs0 ov f1 p e0 h acc f0 h b - : this bit location is reserved bit manipulation is available bit manipulation is not available
gms97c1051/l1051 8-bit cmos microcontroller hyundai microelectronics 26 table 3 . sfr lists and their addresses symbol name address * acc * b dph dpl * psw sp accumulator b register data pointer high byte data pointer low byte program status word stack pointer e0 h f0 h 83 h 82 h d0 h 81 h * ie * ip interrupt enable control interrupt priority control a8 h b8 h * p1 * p3 port 1 port 3 90 h b0 h * tcon th0 tl0 * tmod timer/counter control timer/counter 0 high bytes timer/counter 0 low bytes timer/counter mode control 88 h 8c h 8a h 89 h * = bit addressable sfr timer/counter 0 the gms97c1051/l1051 has one 16-bit timer/ counter register : timer0 . as a timer, the register is incremented every machine cycle. thus, the register counts machine cycle. since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. as a counter, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin p3.4/t0. since 2 machine cycles are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. external inputs p3.2/int0 and 3.3/int1 can be programmed to function as a gate to facilitate pulse width meas- urements. timer/counter 0 can be used in four operating modes as listed in table 4 . figure 3 illustrates the input clock logic. table 4 . timer / counter 0 operating modes mode description tmod gate c/t m1 m0 0 8-bit timer/counter with 5-bit prescaler 00 1 16-bit timer/counter 01 2 8-bit auto-reload timer/counter 10 3 (timer 0) tl0 is an 8-bit timer/counter controlled by the standard timer 0 control bits, th0 is an 8-bit timer 11
8-bit cmos microcontorller gms97c1051/l1051 hyundai microelectronics 27 figure 3 . time/counter 0 input clock logic interrupt system the gms97c1051/l1051 provides 3 interrupt sources ( two external interrupts and timer inter- rupt ) with two priority levels. figure 4 gives a general overview of the interrupt sources and illus- trates the request and control flags. a low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low priority interrupt. a high-priority interrupt cannot be interrupted by any other interrupt source. if two requests of different priority levels are re- ceived simultaneously, the request of higher priority is serviced. if requests of the same prior- ity level are received simultaneously, an internal polling sequence determines which request is serv- iced. thus within each priority level there is a second priority structure determined by the polling sequence like table 6 . figure 4 . interrupt request sources it0 tcon.0 tcon.1 ie0 ex0 ie.0 px0 ip.0 p3.2/ int0 ea ie.7 it1 tcon.2 tcon.3 ie1 ex1 ie.2 px1 ip.2 p3.3/ int1 tf0 tcon.5 timer 0 overflow et0 ie.1 pt0 ip.1 high priority low priority fosc 12 p3.4/t0 max fosc/24 tr 0 tcon gate tmod =1 1 & 0 1 fosc/12 timer 0 input clock control c/t tmod p3.2/int0 p3.3/int1
gms97c1051/l1051 8-bit cmos microcontroller hyundai microelectronics 28 table 5 . interrupt sources and their corresponding interrupt vectors interrupt source vector address external interrupt 0 timer0 external interrupt 1 system reset ie0 tf0 ie1 rst 0003h 000bh 0013h 0000h table 6 . interrupt priority-within-level interrupt source priority external interrupt 0 timer0 interrupt external interrupt 1 ie0 tf0 ie1 highest lowest restrictions on certain instructions the gms97c1051/l1051 is an economical and cost- effective member of hyundai microelectronics growing family of microcontrollers. it contains 1kbytes of eprom program memory. it is fully compatible with the mcs-51 architecture, and can be programmed using the mcs-51 instruction set. how- ever, there are a few considerations one must keep in mind when utilizing certain instructions to program this device. 1. branching instructions: lcall, ljmp, acall, ajmp, sjmp, jmp @a+dptr these unconditional branching instructions will ex- ecute correctly as long as the programmer keeps in mind that the destination branching address must fall within the physical boundaries of the program memory size (locations 00h to 3ffh for the gms97c1051/l1051). violating the physical space limits may cause unknown program behavior. cjne [...], djnz [...], jb, jnb, jc, jnc, jbc, jz, jnz with these conditional branching instructions the same rule above applies. again, violating the memory boundaries may cause erratic execution. for applications involving interrupts the normal inter- rupt service routine address locations of the 80c51 family architecture have been preserved. 2. movx-related instructions, data memory: the gms97c1051/l1051 contains 64 bytes of internal data memory. thus, in the gms97c1051/l1051 the stack depth is limited to 64 bytes, the amount of avail- able ram. external data memory access is not supported in this device, nor is external program memory execution. therefore, no movx [...] in- structions should be included in the program. a typical 80c51 assembler will still assemble instruc- tions, even if they are written in violation of the restric- tions mentioned above. it is the responsibility of the controller user to know the physical features and limi- tations of the device being used and adjust the instruc- tions used correspondingly.
8-bit cmos microcontorller gms97c1051/l1051 hyundai microelectronics 29 idle mode in idle mode, the cpu puts itself to sleep while all the on-chip peripherals remain active. the mode is in- voked by software. the content of the on-chip ram and all the special functions registers remain unchanged during this mode. the idle mode can be terminated by any enabled interrupt or by a hardware reset. p1.0 and p1.1 should be set to 0 if no external pullups are used, or set to 1 if external pullups are used. it should be noted that when idle is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. on-chip hardware inhibits access to internal ram in this event, but access to the port pins is not inhibited. to eliminate the possibility of an unexpected write to a port pin when idle is terminated by reset, the instruc- tion following one that invokes idle should not be one that writes to a port pin or to external memory. power down mode gms97c1051/l1051 have two power saving modes, idle and power down. the bits pd and idle of the register pcon select the power down mode and the idle mode, respectively. if 1s are written to pd and idle at the same time, pd takes precedence. table 7 gives a general overview of the power saving modes. in the power down mode of operation, v cc can be re- duced to minimize power consumption. it must be ensured, however, that vcc is not reduced before the power down mode is invoked, and that vcc is restored to its normal operating level, before the power down mode is terminated. the reset signal that terminates the power down mode also restarts the oscillator. the reset should not be activated before vcc is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. ( similar to power-on reset ). table 7 . power saving modes overview mode ex. instruction to enter to terminate remarks idle mode orl pcon, #01h enabled interrupt, hardware reset - cpu is gated off - cpu status registers maintain their data. - peripherals are active power-down mode orl pcon, #02h hardware reset - oscillator stops - contents of on-chip ram and sfrs are maintained - reset redefines all the sfrs but does not change the on-chip ram
gms97c1051/l1051 8-bit cmos microcontroller hyundai microelectronics 30 programming the eprom the gms97c1051/l1051 is programmed by using a modified quick-pulse programming tm algorithm. it differs from older methods in the value used for v pp (programming supply voltage) and in the width and number of the p3.2( prog ) . the gms97c1051/l1051 contains two signature bytes that can be read and used by an eprom pro- gramming system to identify the device. the signature bytes identify the device as an manufactured by hme. table 8 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the security bits. the circuit con- figuration and waveforms for quick-pulse programming are shown in figures 5 and figure 8. figure 6 shows the circuit configuration for normal program memory verification. eprom programming and verification internal address counter : the gms97c1051/l1051 contains an internal eprom address counter which is always set to 03ffh on the rising edge of rst after setting p3.0 to h and is ad- vanced by applying continuous level transition to pin p3.0. programming algorithm : to program the gms97c1051/l1051, the following sequence is recommended. 1. power-up sequence apply power between v cc and gnd pins with crystal oscillation. set p3.0 to h. set rst to gnd. with all other pins floating, wait for greater than 10ms. 2. set pin rst to h and pin p3.2 to h. 3. apply the appropriate combination of h or l logic levels to pins p3.3, p3.4, p3.5, p3.7 to select one of the programming operations shown in the eprom programming modes. ( table 8 ). to program and verify the array 4. the p3.0 level is pulled l and apply data for code byte at location 0000h to p1.0 to p1.7 5. raise rst to 12.75v to enable pr ogramming. 6. the p3.2( prog ) is pulsed low 10 times as shown in figure 8 . each programming pulse is low for 100us( 10us) and high for a minimum of 10us. 7. to verify the programmed data, lower rst from 12.75v to logic h level and set pins p3.3 to p3.7 to the appropriate levels. output data can be read at the port p1 pins. at this time p3.0 should not be changed. 8. to program a byte at the next address location, p3.0 level transition is needed to advance the internal address counter. apply new data to the port p1 pins. 9. repeat step 5 through 8, changing data and advancing the address counter for the entire 1k bytes array. program verify : if lock bits lb1 and lb2 have not been programmed, code data can be read back via port p1 pins. 1. set the internal address counter to 03ffh by bringing rst from l to h and reset the internal address counter to 0000h by bringing p3.0 from h to l. 2. apply the appropriate control signals for read code data to pins p3.3, p3.4, p3.5, p3.7 and read the output data at the port p1 pins. 3. the p3.0 level transition is taken to advance the internal address counter. 4. read the next code data byte at the port p1 pins. 5. repeat step 3 and 4 until the entire array is read. program memory lock bits the two-level program lock system consists of 2 lock bits and a 32-byte encryption array which are used to protect the program memory against software piracy. encryption array : within the eprom array are 32 bytes of encryption array that are initially unprogrammed (all 1s). every time that a byte is addressed during a verify, address lines are used to select a byte of the encryption array. this byte is then exclusive-nored (xnor) with the code byte, creating an encrypted verify byte. the algorithm, with the array in the unprogrammed state (all 1s), will return the code in its original, un- modified form. it is recommended that whenever the encryption array is used, at least one of the lock bits be programmed as well.
8-bit cmos microcontorller gms97c1051/l1051 hyundai microelectronics 31 lock bit protection modes program lock bits lb1 lb2 protection type 1 u u no program lock features. 2p u further programming of the eprom is disabled. 3p p same as mode 2, also verify is disabled. reading the signature bytes : the signature bytes are read by the same procedure as a normal verification of locations 000h and 001h, except that p3.5 and p3.7 need to be pulled to a logic low. manufacturer id: (00h) = e0h ( indicates manufactured by hei ) device id: (01h) = 16h ( indicates gms97c1051/l1051 ) u : unprogrammed, p : programmed eprom programming modes table 8 . eprom programming modes mode rst p3.2/ prog p3.3 p3.4 p3.5 p3.7 read signature 1 1 0 0 0 0 program code data vpp 0 1 1 1 verify code data 1 1 0 0 1 1 pgm encryption table vpp 0 1 0 1 pgm encryption bit1 vpp 1 1 1 1 pgm encryption bit vpp 1 1 0 0 notes:1. '0' = valid low, '1' = valid high for that pin. 2. vpp = 12.75 v 0.25 v 3. vcc = 5 v 10 % during programming and verification. 4. p3.2/ prog receives 10 programming pulses while vpp is held at 12.75v. each program- ming pulse is low for 100us ( 10us) and high for a minimum of 10us.
gms97c1051/l1051 8-bit cmos microcontroller hyundai microelectronics 32 figure 5. programming the eprom memory p3.0 p3.2 p3.3 p3.4 p3.5 p3.7 v cc p1 pgm data vpp xtal2 gnd to increment address counter see eprom programming 4~6mhz modes tables prog 5v gms97c1051 rst xtal1 figure 6. verifying the eprom memory p3.0 p3.2 p3.3 p3.4 p3.5 p3.7 v cc p1 pgm data 5v 5v xtal2 gnd to increment address counter see eprom programming 4~6mhz modes tables 5v gms97c1051 rst xtal1 eprom programming and verification characteristics table 9 . eprom programming and verification characteristics parameter symbol min max units programming supply voltage v pp 12.5 13.0 v programming supply current i pp 50 ma oscillator frequency 1 / t clcl 46mhz address setup to prog low t avgl 48 t clcl data setup to prog low t dvgl 48 t clcl data hold after prog t ghdx 48 t clcl p3.4 ( enable ) high to v pp t ehsh 48 t clcl v pp setup to prog low t shgl 10 us v pp hold after prog t ghsl 10 us prog width t glgh 90 110 us prog high to prog low t ghgl 10 us p3.4 ( enable ) low to data valid t elqv 48 t clcl data float after p3.4 ( enable ) t ehqz 0 48 t clcl t a = 21 to 27 , v cc = 5.0 10%
8-bit cmos microcontorller gms97c1051/l1051 hyundai microelectronics 33 eprom programming and verification waveforms figure 7 . eprom programming and verification data in data out address (n+1) address (n) t ehsh t ghgl vpp logic 1 logic 0 rst (vpp) p3.4 (enable) port1 p3.2 (prog) p3.0 t ghsl t dvgl t ghdx t glgh t avgl t shgl t elqv t eh q z programming verification figure 8 . programming waveform p3.2/ prog 10 pulses 100 10 10 min p3.2/ prog
gms97c1051/l1051 8-bit cmos microcontroller hyundai microelectronics 34 absolute maximum ratings ambient temperature under bias (t a .)....................... - 40 to + 85 storage temperature (t st ) ..... -65 to + 150 voltage on v cc pin with respect to ground(v ss ).........-0.5v to +6.6v voltage on any pin with respect to ground(v ss )... -0.5v to v cc +0.5v input current on any pin during overload condition.........-10ma to +10ma absolute sum of all input current during overload condition................... | 100 ma | note : stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for longer periods may affect device reliability. during overload conditions (v in > vcc or v in < vss ) the voltage on vcc pins with respect to ground (vss) must not exceed the values defined by the absolute maximum ratings.
8-bit cmos microcontorller gms97c1051/l1051 hyundai microelectronics 35 d.c. characteristics (5v version) vcc = 4.25v to 5.5v, vss= 0v, t a = 0 o c to 70 o c for the gms97c2051/c1051 parameter symbol limit values unit test min max condition input low voltage v il -0.5 0.2vcc-0.1 v input high voltage (except xtal1, rst) v ih 0.5vcc-0.1 vcc+0.5 v input high voltage (xtal1, rst) v ih1 0.7vcc vcc+0.5 v output low voltage (ports 1,3) v ol 0.45 v i ol =10ma,vcc=5v output high voltage (ports 1,3) v oh 2.4 0.75vcc 0.9vcc vi oh = -80ua, vcc=5v 10% i oh = -30ua i oh = -12ua logical 0 input current (ports 1,3) i il -50 ua v in =0.45v logical 1-to-0 transition current (ports 1,3) i tl -750 ua v in =2v input leakage current (port p1.0, p1.1) i li 1ua ua 0 gms97c1051/l1051 8-bit cmos microcontroller hyundai microelectronics 36 d.c. characteristics (3v version) vcc = 2.7v to 3.6v, vss= 0v, t a = 0 o c to 70 o c for the gms97l2051/l1051 parameter symbol limit values unit test min max condition input low voltage v il -0.5 0.2vcc-0.1 v input high voltage (except xtal1, rst) v ih 0.5vcc-0.1 vcc+0.5 v input high voltage (xtal1, rst) v ih1 0.7vcc vcc+0.5 v output low voltage (ports 1,3) v ol 0.45 v i ol =6ma,vcc=2.7v output high voltage (ports 1,3) v oh 0.75vcc 0.9vcc vi oh = -30ua i oh = -12ua logical 0 input current (ports 1,3) i il -50 ua v in =0.45v logical 1-to-0 transition current (ports 1,3) i tl -750 ua v in =2v input leakage current (port p1.0, p1.1) i li 1ua ua 0 8-bit cmos microcontorller gms97c1051/l1051 hyundai microelectronics 37 external clock drive waveforms t chcx t clcl t clcx t chcx t clch 0.7 v cc 0.2 v cc - 0.1v 0.45v v cc - 0.5 v t chcl external clock drive symbol parameter gms97l2015/l1051 gms97c2051/c1051 min max min max units 1/t clcl oscillator frequency 0 12 0 24 mhz t clcl clock period 83.3 41.6 ns t chcx high time 30 15 ns t clcx low time 30 15 ns t clch rise time - 20 - 20 ns t chcl fall time - 20 - 20 ns ac testing input/output waveforms (1) v cc - 0.5v 0.45v 0.2v cc + 0.9v test points 0.2v cc - 0.1v note: 1. ac inputs during testing are driven at v cc - 0.5v for a logic 1 and 0.45v for a logic 0. timing measurements are made at v ih min. for a logic 1 and v il max. for a logic 0. float waveforms (1) v load + 0.1v v load v load - 0.1v v ol + 0.1v v ol + 0.1v timing reference points note: 1. for timing purposes, a port pin is no longer floating when a 100mv change from load voltage occurs. a port pin begins to float when a 100mv change from the loaded v oh /v ol level occurs.
gms97c1051/l1051 8-bit cmos microcontroller hyundai microelectronics 38 package dimension 20 pdip 20 sop unit : mm ( inch )
8-bit cmos microcontorller gms97c1051/l1051 hyundai microelectronics 39 ordering information speed ( mhz) power supply ordering code package operation range 12 2.7v to3.6v gms97l1051 20 pdip gms97l1051-d 20 sop 4.25v to 5.5v gms97c1051 20 pdip commercial gms97c1051-d 20 sop (0 to 70 ) 24 4.25v to 5.5v gms97c1051-24 20 pdip GMS97C1051-24D 20 sop package type 20 pdip 20 lead, 0.300 wide, plastic dual inline package (pdip) 20 sop 20 lead, 0.300 wide, plastic gull wing small outline (sop)

▲Up To Search▲

Price & Availability of GMS97C1051-24D

	To Download GMS97C1051-24D Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .